Battery operated devices, such as mobile devices, based on bulk planar FET ASIC designs use a variety of techniques for implementing different operating modes having different VDD requirements. For example, using 2G and 3G cellular devices as an example, there are different VDD requirements for standby mode where a lower VDD is used to reduce leakage, talk mode where a higher VDD is needed to increase performance but lower switch power is desired, and high speed data applications where maximum operating speed is required.
Various techniques for providing these multi-operating modes exist in bulk planar designs. For example, complex multi-Vth designs may be utilized, but this approach requires additional masks and thus increases cost. For a single Vth design, voltage scaling techniques such as adaptive voltage scaling (AVS) and dynamic voltage and frequency scaling (DVFS) techniques have also been used but these techniques cannot cover a wide range of the speed-power envelope, i.e., they cannot extend the performance boost or leakage reduction too far from the nominal operating point. Adaptive body bias, where the body bias is reduced to reduce leakage current, is yet another technique, but this technique can only be used to reduce the chip speed by increasing the threshold voltage. It is possible to slightly boost performance using adaptive body bias in bulk planar designs by lowering the threshold voltage but with the risk of forward biasing the transistor. Finally, some designs use a header switch, such as a PMOS power switch, to shut down the entire chip in certain modes, but this approach increases area and decreases speed due to the voltage drop across the switch.